Operating Systems and Systems Programming (CS 140), Stanford, Winter 2011

Implemented Threading and Multiprogramming with special focus on synchronization protocols (locks and semaphores).
Added Virtual Memory design to enable loading multiple memory intensive programs simultaneously.
As a final touch, implemented actual file system to make it full-fledged Operating Systems.

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Introduction to Digital Systems (EE 273), Stanford, Winter 2011

Designed a 640Gbps router system architecture that interconnected 16 line cards via crossbar cards with redundancy.
Implemented design with optimal balance between cost, speed, reliability, area, routing complexity and practical feasibility while providing functional correctness.
Connected 16 line cards through an orthogonal architecture to the primary and redundant crossbar card; each line card possessed two data cards with lines operating at a frequency of 9.375 GBps.

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Computational Molecular Biology, (BIOC 218), Stanford University, Winter 2010

Researched about different techniques to estimate Copy Number Variants (CNV) location and analyzed the importance of CNV estimation.
Performed comparative analysis of their computation frequency and performances.

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Design Projects in VLSI systems (EE 272), Stanford, Spring 2010.

Synthesized, placed and routed complete ASIC design using 90nm CMOS Technology.
Employed low power Verilog coding techniques with hardware reusage and parallelism.

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Parallel Computer Architecture and Programming (CS 315A), Stanford University, Spring 2010

Designed an ASIC implementation for Smith Waterman Algorithm for 64 bit queries using Verilog and revised the design using more efficient power saving techniques.
Performed Placement & Route on the synthesized version.
Employed thread pool scheduling and blocked parallelism version, to implement a parallel version of the algorithm.

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Computer Systems Architecture (EE 282), Stanford University, Spring 2010

Programmed JPEG encoding on three processors in the OMAP-3430 chip in the Nokia N900 smartphone.
Programmed vector instructions in Neon Processor and improved the speed by 1.3 times.

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Digital MOS Integrated Circuits (EE 313), Stanford University, Winter 2009

Designed a complete memory model for SRAM with decoder, sense-amplifiers and resistor models.
Applied power saving techniques by divided wordline, patitioned bitlines and designing write circuitry.
Designed a replica model with variable delay for SAE signals generation using SPICE.

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Introduction to VLSI Systems (EE 271), Stanford University, Autumn 2009

Phase I: Understanding the golden model and completing the C++ code.
Phase II: Detecting and fixing the bugs and speeding up the design using Parallelism in comparison, Booth multiplier with Carry Save Addition.
Phase III: Improving the model to achieve maximum throughput requirement with minimum power and area requirements; using bubble smashing, FSM halt cycle removal, back face culling, ceiling functions and triangle merging.

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Programming Abstractions, (CS 106B), Stanford University, Autumn 2009

First prize for coding for a Random Writer that generated Shakespearean Sonnets with partial iambic pentameter and rhyme scheme ababcdcdefefgg.
Path Finder using Dijkstra's algorithm and minimal spanning tree using Kruskal's algorithm; Boggle Game with embedded graphics library and Basic Interpreter are few assignments completed as part of the course requirement.

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ST Microelectronics Lab, BITS-Pilani. Mentor : Mr.Anurup Mitra, Jan-Dec 2008

Analyzed and implemented the latest industrial architectures.
Performed detailed study of transient responses and dependency factors.
Designed techniques to achieve the best stability and transient responses.

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Clean Room Laboratory CEERI, Pilani, under the guidance of Dr.Eranna, Scientist ‘F’, Aug-Dec, 2008

Understood various Oxidation techniques and kinetics dependence.
Compared practical results with theory.
Performed in-depth study of various oxide parameters using latest equipments.

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Analog and Digital VLSI Design Course Project
Mentor: Dr. Anu Gupta, EEE Dept., BITS-Pilani

Understood various multiplication algorithms including Redundant Binary tree architecture.
Implemented design using Verilog coding, Leonardo spectrum, RC compiler and other EDA tools.

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Analog and Digital VLSI Design Course Project
Mentor: Dr. Anu Gupta, EEE Dept., BITS-Pilani

Understood and designed a Digital to Analog converter (I-V type).
Implemented design using Pspice and Cadence Virtuoso.

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Microprocessor Programming and Interfacing Course Project
Mentor: Dr. S.Gurunarayanan EEE Dept., BITS-Pilani

Understood and designed a model for a newspaper vending machine·
Innovated an unique model for weight sensor and memory mapping.

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APOGEE, All India Technical Festival, BITS-Pilani

My second major project was a team effort to implement the “Smart Pen” concept, where anything written with the smart pen on any surface would be captured and stored for later display or live presentation on slides. Our aim was to shift the sensor circuitry to the pen nib and the memory and wireless transmission section to the back end. This would bolster the portability reducing the cost and thus, promoting the launch of the product for challenged individuals and usage in lectures. Apart from assisting with the soldering of the laser sensor circuits and modelling of the structure, my role was to implement the software part in C/C++. Employing the concept of capturing mouse click, I tried tracing the motion of pen nib. Using GetCursor location and similar functions, I attempted at getting the coordinates and storing them into a database file that could be compressed and used later. Difficulty arose when continuity of characters had to be maintained and recognition of characters was employed to assist the user. The hardware side involved fixing the laser’s orientation and sensors to record the reflected beam along with transferring the recorded data to laptop or computer. Our team succeeded in making the wired version and we presented our pen in the All India Technical Festival, APOGEE, BITS-Pilani.

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IITB TechFest , IIT Bombay, 2007

Participated in the CRO 2.0 competition to make a game of ping-pong on the CRO screen using microcontrollers.
Implemented the design through resistor ladder and learnt basic soldering techniques.

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SSI-IT Centre's Project for TamilNadu Special Police, 2006

Employed ASP.Net programming language to design Library Management Protocol.

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